Prior art FIG. 1 illustrates both a strobe signal 102 and a data signal 104 for use in association with a typical sampling circuit. In use, the strobe signal 102 (e.g. signal edge, etc.) of the sampling circuit serves as a clock event for triggering the sampling of the data signal 104. Typically, such sampling circuit includes a flip-flop or the like for carrying out such sampling functionality.
In order to operate correctly, the data signal 104 typically exhibits a setup time 106 and a hold time 108, in the manner shown. In particular, the setup time 106 represents a time relative to the strobe signal 102 during which the data signal 104 to the sampling circuit (or component thereof) must remain stable in order to ensure that the sampled output is correct. Similarly, the hold time 108 represents a time following the strobe signal 102 during which the data signal 104 to the sampling circuit (or component thereof) must remain stable in order to guarantee the correct sampled output.
The foregoing setup/hold time constraints typically mandate a “minimum time budget” that must be allocated in association with the data signal 104. Such minimum time budget, in turn, constrains a rate at which the data signal 104 may be sampled, thus making it difficult to increase the speed of an associated system.